The present invention relates generally to semiconductor devices and more integrated circuits and, particularly, to technical expedients implemented for protecting the active and/or passive components of the integrated circuits from the possibility of being accidentally damaged by electrical discharges of an electrostatic origin during the fabrication, assembly and/or handling of the device or integrated circuit.
Great technological advances in the field of the fabrication techniques of integrated circuits have permitted a great increase in the density of the circuits and the performances of the single circuit components but, at the same time have often cause a greater sensitivity of some of these components to damages attributable to accidental electrical discharges of an electrostatic origin.
In this respect, it is known that floors, glasses, containers and carriers for handling wafers, plastic bags and plastic tubes for carrying the devices are highly dangerous materials because of the relatively high potentials which these materials may easily assume (up to 30 kV).
Moreover, the operator himself in handling devices may induce an electrical discharge of an appreciable value.
The use of particular antistatic materials for flooring, for bench tops and other expedients which ensure a continuous drainage of electrical charges by dispersing them toward ground are indispensable in order to prevent discharges of a high intensity.
However, even a most sophisticated antistatic system is insufficient in preventing accidental damages, especially in the case of particularly sensitive components which show failures with voltages on the order of 100-400 V. In these instances a circuital type of intervention becomes necessary; moreover, even intrinsically sturdy semiconductor structures, if handled in environments not particularly equipped so as to prevent triboelectric effects, may be subject to failure.
From the point of view of resistance to damage from electrostatic discharges, each particular type of device shows a proper interval of voltages beyond the limits of which the discharge, by a voltage effect in MOS devices or by a current effect in bipolar devices, causes failure or degradation.
With a high scale of integration and therefore with ever smaller geometries, the problem, originally limited to the domain of MOS devices, has presented itself also in the domain of bipolar integrated circuits and of course also in the so-called mixed processes which realize MOS and bipolar components on the same monolithic substrate (chip).
Electrostatic discharges involving base-emitter junctions in small area transistors may cause irreversible damage, and may cause irreversible puncturing of the thin layer of gate oxide in MOS components as well as in integrated capacitors.
In integrated circuits the problem is generally tackled by making protection structures essentially acting as a limiting diode between each input pad of the integrated circuit and, respectively the common ground (or V.sub.SS) and the common supply node (or V.sub.DD). Commonly such a protection structure is an appropriate junction connected between the input pad and the respective ground or supply node. In the case of an output pad, the junction may be that of the integrated output device itself or of the output stage of the circuit.
Such protection systems have been amply debated and analyzed in terms of their "efficiency" and sturdiness as well as in terms of the area requirement of the integrated protection structures and in terms of the speed of intervention, quantified in terms of the RC constant measured between the relative terminal and the ground (V.sub.SS) or supply (V.sub.DD) terminal.
In known analyses of the problem and of state-of-the-art technical proposals for ensuring immunity from damage of devices when subjected to electrostatic discharges of several thousands Volts, the attention has been almost exclusively directed to reducing as much as possible the intrinsic series resistance and the area requirement of the protection diode deployed to provide the necessary discharge path of the negative electric charge (i.e. toward ground or V.sub.SS) or of the positive electric charge (i.e. toward the positive supply node or V.sub.DD) which may accidentally become applied to the relative input or output pin (or pad) of the integrated circuit.
The location of the protection diode or diodes is almost exclusively adjacent to the pad itself, if not at least partially underneath the metallized area of the pad to which one terminal of the protection diode is connected in order to save useful chip area. The other terminal of the diode is connected to adjacent metal tracks (i.e. supply or V.sub.DD) or ground (or V.sub.SS).
On the other hand, with such typical layouts, remarkable differences among "holding" levels with respect to electrostatic discharges for different pins of the same integrated circuit are often observed, especially among different input pins of the circuit. These differences can not be accounted for in terms of the normal "spread" of parameters of distinct similar integrated devices and of distinct protection diodes.
Obviously it is the holding level of the pin experimentally found "weaker" which determines a positive or negative result of a quality control test conducted on a particular integrated circuit according to applicable standard specifications.